Kai ChenOn October 8, GlobalFoundries agreed to provide TSMC with $2 billion in silicon-interposer production capacity over five years at its Malta, New York, facility. TSMC makes leading-edge logic chips; it had turned to another foundry for a component that connects them inside an AI accelerator.
Key takeaways
- GlobalFoundries agreed on October 8 to provide TSMC with $2 billion in silicon-interposer production capacity over five years from Malta, New York.
- TSMC says its CoWoS packaging capacity is growing at an 80% compound annual rate, while Nvidia has reserved most of that capacity.
- Nvidia’s H200 uses HBM3E rated at 6.5Gbps per pin, compared with 5.3Gbps per pin for the H100’s HBM3.
- GlobalFoundries previously received $1.5 billion in CHIPS Act grants and $1.6 billion in loans for a new Malta fab and an expansion of Fab 8.
- Sources said TSMC urged customers to seek N2 allocations as far out as the second quarter of 2027, with large allotments nearly sold out for the following two years.
An accelerator also needs memory, substrates and packaging capacity to arrive in time for integration. The Malta agreement secures one part of that schedule. It does not establish that every designer contracts this way, or that another foundry can assemble a qualified alternative for any given chip.
More of an accelerator’s performance rests outside the die
Intel demonstrated Foveros 3D stacking in 2018, placing logic chips atop one another. Nvidia’s H200 made the contribution of nearby memory visible in 2023: it used HBM3E rated at 6.5Gbps per pin, up from the H100’s HBM3 at 5.3Gbps per pin. The connections among components and the memory they can use help determine what the finished accelerator can do.
SK hynix completed HBM4 development in 2025; Samsung said it began commercial HBM4 shipments in 2026 while seeking Nvidia’s business. Chipmakers are working on the connections too. Intel demonstrated an optical compute-interconnect chiplet in 2024, while TSMC was reportedly developing an “EMIB-like” packaging method in 2026. Neither project establishes interchangeable production capacity. Each addresses the task of making separate components function as one product.
Nvidia reserved the step after fabrication
TSMC says its CoWoS packaging capacity is growing at an 80% compound annual rate, while Nvidia has reserved most of it. Both can be true: a customer planning accelerator generations needs access to the packaging line, not merely confidence that the line will grow. Nvidia’s reservation establishes the pressure on CoWoS for a major buyer; it does not show that packaging has displaced wafer fabrication as the industry’s only constraint.
Other suppliers face their own scheduling pressure. Industry executives said major memory makers were at or near full capacity and 2026 production slots were almost sold out because of AI demand. Ibiden, a major Nvidia package-substrate supplier, said it might need to expand capacity. An accelerator maker needs the resulting parts at the same time, so a missing component can delay a finished system even when the others are available.
Long-term chip-capacity agreements are not new. Qualcomm signed a multibillion-dollar production agreement with GlobalFoundries in 2022, and GM arranged exclusive US capacity for key suppliers in 2023. The GlobalFoundries–TSMC contract applies that purchasing logic to silicon interposers. It documents one large packaging-layer commitment, rather than an industry-wide contract standard.
Wafer queues still set limits on the schedule
AMD CEO Lisa Su said the company wants to substantially increase supply in 2027 and needs more advanced wafer capacity; she met with TSMC and Foxconn while pursuing that goal. TSMC’s N3 logic capacity has also been identified as a major AI-industry constraint. Packaging has joined the bottleneck list rather than removed the wafer from it.
Sources said TSMC urged clients to seek N2 production allocations as far out as the second quarter of 2027, with large allotments nearly sold out for the following two years. Apple reportedly faced more competition for TSMC capacity amid AI demand, while Qualcomm launched flagship Snapdragon products built on TSMC’s 2nm process. Available wafer and packaging slots help determine which customers’ plans have a manufacturing path.
Alternative packaging routes still need customers
Intel’s advanced-packaging business has grown, and the company has reportedly discussed packaging services with Google and Amazon. TSMC was reportedly close to finalizing specifications for panel-level packaging to meet AI-chip demand. Intel’s talks are not customer contracts, and TSMC’s reported method is not installed capacity. Both show where manufacturers are putting development effort.
Specialist assemblers have a role too. ASE Technology, described as the world’s largest chip-packaging and testing firm, opened a Penang plant in 2025 as part of its largest overseas expansion. Such factories give designers possible routes, but a customer still has to qualify the memory, substrate and interconnect with the package it intends to buy.
A domestic interposer is one part of a domestic system
GlobalFoundries’ Malta agreement places interposer production in New York. The company had already received $1.5 billion in CHIPS Act grants and $1.6 billion in loans for a new Malta fab and an expansion of Fab 8. Those awards support a broader US buildout; the record does not say they were earmarked for this interposer contract. TSMC’s US plans separately include two advanced-packaging facilities in Phoenix alongside additional fab phases and an R&D center.
Frequently asked questions
How much interposer capacity does the $2 billion agreement actually buy?
The agreement’s disclosed value and five-year term do not state a wafer count, interposer count, capacity share, or delivery schedule. The $2 billion figure therefore cannot be converted into a specific annual output figure from the information available.
Does the agreement identify which TSMC products or end customers will use GlobalFoundries-made interposers?
No. The disclosed agreement names TSMC and GlobalFoundries and specifies silicon-interposer capacity at Malta, but it does not identify a TSMC product line, accelerator design, or downstream customer allocation.
What share of TSMC’s CoWoS capacity has Nvidia reserved?
The piece says Nvidia has reserved “most” of TSMC’s CoWoS capacity, but it provides no percentage, volume, or contract duration. That makes the scale of Nvidia’s reservation directionally clear but not precisely measurable.
When could Intel, ASE, or TSMC panel-level packaging become a qualified substitute for a given AI accelerator?
No timetable is disclosed. Intel’s reported discussions with Google and Amazon are not contracts, TSMC’s panel-level work was still at the specification stage, and the piece provides no qualification dates or production volumes for alternative routes.
HBM bandwidth cited for Nvidia accelerators
| Accelerator | Memory | Rated bandwidth per pin |
|---|---|---|
| H100 | HBM3 | 5.3Gbps |
| H200 | HBM3E | 6.5Gbps |
Neither location alone makes a complete AI accelerator domestic. A designer still needs compatible capacity for logic, memory, substrates and final integration. The $2 billion Malta agreement secures an interposer supply commitment, but it cannot by itself qualify a second route for a customer’s design. A buyer with a spare wafer slot still needs a package it can ship.