TSMC details its roadmap: a high volume 3nm chip production starting in H2 2022, with five 3nm-class N3 node iterations, and 2nm-class N2 introduction in 2025
TSMC had already begun installing 3nm fabrication lines and repeatedly set H2 2022 as the target for volume output; its 4nm process was also slated to move from risk production into mass production in 2022. The new roadmap adds a longer product cadence to those manufacturing milestones.
Rather than treating 3nm as a single handoff, TSMC maps five N3-class iterations before a 2nm-class transition in 2025. That matters because node roadmaps commit process development and capacity planning years ahead of end-product launches.
First-order effects
TSMC must sustain high-volume 3nm output while developing five successive N3 variants, extending the commercial life of its 3nm-class manufacturing platform.
The planned 2025 N2 introduction establishes TSMC's next process transition after the N3 family, rather than leaving a gap after initial 3nm production.
Second-order effects
Customers planning chips around TSMC processes gain a clearer sequence from 4nm and initial 3nm production to later N3 variants and N2, making process-node selection a multigeneration planning decision.
TSMC's fabrication and equipment planning is tied to overlapping ramps: 4nm entering mass production, 3nm scaling, and N2 development proceeding in parallel.
Third-order effects
The roadmap points toward leading-edge foundry competition being decided by sustained node-family iteration and overlapping production ramps, not merely by reaching a headline node first.
If TSMC executes the sequence, access to leading-edge capacity will remain governed by long lead times between process development, fab installation, and volume production.
The trend: Leading-edge foundries are turning individual process-node launches into multiyear platform roadmaps that coordinate technology iteration with capacity buildouts.
I ‘hate’ to break it to the Intel naysayers, but for the last *two years* Intel hasn't had *any* process delays. In that time, both TSMC and Samsung have slipped. Who's got the better execution? Surely not TSMC with its 1.1x N2 shrink.
@WrenIndian @witeken Oh FFS. This is because ASML can't deliver high NA EUV machines fast enough to roll in better lithography immediately. Intel will face exactly the same constraint! https://www.anandtech.com/...
TSMC discloses their N2 node for 2026 products will feature >1.1x chip density improvement over N3E (50% Logic, 30% SRAM, 20% Analog). Transistor Area Scaling grinds to a crawl! https://twitter.com/...
Delivering a major update to their roadmap, TSMC today has revealed that they are developing a total of 5 versions of their N3 process. Joining N3 will be N3E, N3P, N3S, and N3X, giving more design options, as well as FinFlex tech for low-level flexibility https://www.anandtech.c…
As TSMC's last “classic” FinFET node, the N3 family is going to be around for quite a while. As a result, the company is preparing a further 4 versions of the node, for a total of 5 variants of N3 https://twitter.com/...
2/5 TSMC 1. N2 will begin production in 2025 and offer 10-15% speed improvement, or 25-30% power reduction. 2. N2 will be first TSMC node to use GAAFETs, nanosheet-based Gate-All-Around Field-Effect Transistors, a costly change for clients, in time, new design techniques, IP.
4/5 TSMC will expand production capacity for mature and specialty processes 50% by 2025 1. Japan: Kumamoto 300mm plant. Processes: N12, N16, N22, and N28. Up to 45,000 wafer starts per month. 2. Taiwan: Fab 14 in Tainan, Fab 22 in Kaohsiung. 3. China: Nanjing N28 $GFS $UMC $TSM