Intel claims its Intel 4 node, its first to use EUV lithography, offers 21.5% higher frequencies or 40% power reduction vs Intel 7, up to 2x transistor density
Paul Alcorn / Tom's Hardware :
Context & Ripple Effects
This claim lands mid-arc in Intel's long manufacturing rebuild. Back in 2019, Intel's partner laid out a cadence of EUV nodes running through the decade (the shared process roadmap), but Intel 4 is the first node where EUV lithography actually ships into Intel's own numbers — the moment the roadmap stops being a promise and starts being measured against Intel 7 silicon.
The stakes are competitive credibility as much as specs: every subsequent node claim Intel has made builds on this one, from the Sierra Forest and Granite Rapids Xeon efficiency targets to the 18A-based Panther Lake performance-per-watt story.
First-order effects
- Products designed on Intel 4 gain a concrete trade-off dial — 21.5% more frequency at constant power or 40% less power at constant frequency versus Intel 7 — which directly shapes the clock and thermal budgets of Intel's next client and server chips.
- With up to 2x transistor density, Intel can pack more cores or cache per die, feeding directly into the efficiency-per-core claims it later makes for its Xeon lineup.
Second-order effects
- A working EUV node gives Intel Foundry a sellable process floor, setting up the later move to High-NA EUV tools (the first commercial High-NA assembly) as an escalation rather than a leap of faith.
- Rival fabs' per-node gain claims now face a direct apples-to-apples benchmark: Intel is publishing frequency, power, and density deltas against its own prior node, inviting the same scrutiny of competitors' nodes.
Third-order effects
- If each node keeps banking double-digit percentage gains — Intel 4's 40% power cut, then RibbonFET-era efficiency claims — the industry's competition shifts from who has EUV to who compounds it fastest across generations.
- Process-node cadence becomes the binding constraint on product roadmaps: server and client silicon plans (Xeon refreshes, Panther Lake-class parts) inherit their performance ceilings from whatever the fab delivers two to three years earlier.
The trend: Chipmakers are turning lithography transitions into published, quantified per-node contracts — frequency, power, and density deltas — that anchor both their product roadmaps and their foundry pitches.