Intel shares its post-2025 plans for pushing chip performance, including stacking transistors on top of each other to fit 30%-50% more into a given area
Context & Ripple Effects
This announcement closes a loop Intel has been opening for years. The company first demonstrated stacking logic chips atop one another with its Foverus approach back in 2018, then rebuilt its process roadmap around EUV-based Intel 4 and PowerVia backside power delivery, before shipping those gains into 18A-based Panther Lake. The post-2025 plan takes the next logical step: instead of stacking dies, stack the transistors themselves, fitting 30%-50% more into a given area.
First-order effects
- Intel now has a named density lever beyond 18A, giving its foundry customers a visible path past the RibbonFET generation detailed alongside Panther Lake's 50%-at-similar-power claim.
- The plan converts Intel's earlier research-stage work — the gate-all-around and interconnect breakthroughs from its Foundry Technology Research team — into a committed product direction.
Second-order effects
- Combining stacked transistors with PowerVia's backside power delivery lets Intel pitch a differentiated package to foundry customers rather than competing node-for-node on lithography alone.
- Any rival foundry courting the same customers must now answer a vertical-scaling roadmap, not just a shrink cadence, when making density promises for the late decade.
Third-order effects
- If the pattern holds, the industry's density engine shifts from lateral shrinking — where each EUV node buys less — toward vertical integration of transistors, making 3D device stacking the standard measure of process leadership rather than nanometer labels.
The trend: Chip roadmaps are pivoting from lateral transistor shrinking to vertical stacking, with Intel using seven years of packaging and power-delivery groundwork to make 3D devices its post-2025 density bet.