Interview with AMD's CTO, Mark Papermaster, on the launch of Zen 3, its new core complex design and improved power efficiency, and pressure from Arm ecosystem
Dr. Ian Cutress / AnandTech : Tweets: @tdevilfish , @sasamarinkovic , and @ogawa_tter . Thanks: @iancutress Tweets: @tdevilfish : >We have historically have lived in nothing but a competitive environment - we don't expect that to change going forward. Our view is very simply that the best defense is in fact a strong offence - we're not letting up! GRUG SMASH https://twitter.com/... Sasa Marinkovic / @sasamarinkovic : MUST READ interview with AMD's Mark Papermaster and @IanCutress over at AnandTech, Inc. discussing AMD's positioning, performance, and outlook. https://www.anandtech.com/... @ogawa_tter : => “AMD Zen 3: An AnandTech Interview with CTO Mark Papermaster”, @IanCutress , Oct 16, 2020 https://www.anandtech.com/... 34:24 https://www.youtube.com/... +19% IPC 32 MB of L3 cache ? Improving the Utilization of Micro-operation Caches in x86, AMD Res, MICRO 2020 https://twitter.com/... Thanks: @iancutress
Context & Ripple Effects
This interview extends an AnandTech thread that has tracked Papermaster's playbook for years: the 2018 EPYC chiplet strategy Q&A laid out the 7nm CPU die plus 14nm IO die split, and the January 2020 release-schedule interview previewed the cadence Zen 3 now delivers on. The new core complex design — unified eight-core CCX — is the architectural payoff of that chiplet roadmap, and Papermaster frames it explicitly as offense: AMD expects nothing but a competitive environment and isn't letting up.
First-order effects
- The Zen 3 launch puts AMD's new core complex and improved power efficiency directly against Intel across workloads — pressure Papermaster acknowledges is now coming from both x86 rivalry and the Arm ecosystem.
- The unified CCX redesign changes the performance story AMD can tell server and desktop buyers, building directly on the chiplet architecture Papermaster detailed back in the EPYC Q&A.
Second-order effects
- Intel is forced to answer on both fronts: per-core performance against Zen 3's unified cache design and efficiency against AMD's TSMC-based process advantage — the review coverage later bore this out with a 19%+ IPC uplift from Zen 2 and wins across workloads.
- Arm server vendors gain a talking point AMD itself validates: if AMD's CTO names the Arm ecosystem as competitive pressure, Arm-based silicon has crossed into the mainstream server conversation AMD competes in.
Third-order effects
- If the pattern holds, x86 incumbency becomes a two-front contest — Intel behind and Arm ahead — pushing AMD to keep leaning on design efficiency and manufacturing partnerships (TSMC, per the earlier interviews) rather than process leadership alone.
- The recurring Papermaster interview arc — chiplet strategy, release cadence, now Arm pressure — traces AMD's shift from underdog challenger to the company defining x86's competitive pace, a structural reversal from the 2018 EPYC positioning.
The trend: Server and desktop CPU competition is compressing into a two-front race where AMD's design-led cadence pressures Intel from one side while the Arm ecosystem pressures x86 from the other.