Q&A: AMD CTO Mark Papermaster on the company's strategy for its EPYC server processor line and its chiplet approach of combining 7nm CPU dies with 14nm IO dies
Ian Cutress / AnandTech : Thanks: @iancutress
Context & Ripple Effects
This Q&A lands mid-arc in AMD's server rebuild. The company re-entered enterprise silicon with the June 2017 launch of EPYC, topping out at 32 cores and 64 threads per socket, and by August CTO Mark Papermaster had laid out the bet on 7nm over 10nm explicitly framed against Intel's process delays.
What this conversation adds is the mechanism behind that bet: rather than shrinking a monolithic die, AMD splits EPYC into 7nm CPU chiplets paired with 14nm IO dies, letting each function sit on the node that suits it. Papermaster detailing the architecture publicly signals that the chiplet split — not just the node shrink — is the core of the server strategy.
First-order effects
- Server buyers evaluating EPYC get a socket whose compute scales independently of its IO, since only the CPU dies need to move to 7nm while the IO die stays on cheaper 14nm silicon.
- Intel's delayed node roadmap now faces a competitor whose next-generation server parts do not depend on matching Intel's process cadence — the cost-per-core math shifts toward AMD exactly in the segment Papermaster says AMD is targeting for share.
Second-order effects
- AMD's node choices deepen its dependence on TSMC for leading-edge CPU dies, making the foundry relationship a strategic asset — a thread Papermaster picks up directly in later interviews on release schedules and the TSMC partnership.
- Rivals designing monolithic server dies must either adopt their own multi-die approaches or accept a structural cost disadvantage as chiplet designs amortize mask and yield costs across smaller dies.
Third-order effects
- If the pattern holds, server processors become assemblies of function-specific dies on mixed nodes rather than single monolithic chips — decoupling CPU scaling from IO and packaging decisions and resetting how socket-level performance is priced.
- The durability of the approach is visible in the arc itself: the same CTO framing chiplets in 2018 is still describing AMD's node leadership into the 2nm era, suggesting the disaggregation decision outlasted any single product generation.
The trend: Server silicon is moving from monolithic dies to modular chiplets built on leading-edge foundry nodes, with the CPU-to-IO split letting vendors scale compute without waiting on every function to shrink together.