Interview with AMD CTO Mark Papermaster on AMD's release schedule and future products, partnerships with TSMC and Samsung, driving industry standards, and more
Dr. Ian Cutress / AnandTech : Tweets: @anandtech . Thanks: @iancutress Tweets: @anandtech : On the back of a successful 2019, our @IanCutress spent some time with @AMD CTO Mark Papermaster to discuss what it means to be AMD, metrics that drive engineers forward, how IF and CXL play into the plans, and if there's more performance at come. https://www.anandtech.com/... https://twitter.com/... Thanks: @iancutress
Context & Ripple Effects
This interview lands at the start of what became a defining year for AMD: the CTO sat down with AnandTech after a successful 2019 to lay out the release schedule, the dual foundry relationship with TSMC and Samsung, and how Infinity Fabric and CXL fit the roadmap. It extends an arc that began with his 2018 explanation of the EPYC chiplet strategy pairing 7nm CPU dies with 14nm IO dies.
The timing matters because a week later CEO Dr. Lisa Su gave her own wide-ranging Q&A flagging TSMC's tight wafer supply — making this CTO conversation the strategic counterpart to the capacity question. Six years on, Papermaster would tell More Than Moore that AMD became the first customer for TSMC's 2nm process, which retroactively frames this 2020 interview as an early statement of the foundry-lead posture.
First-order effects
- Customers and partners get public visibility into AMD's release cadence directly from the CTO rather than through product launches, with TSMC and Samsung named as the two foundry pillars behind upcoming products.
- AMD positions itself as a standards driver rather than a follower by tying Infinity Fabric to CXL, giving server buyers a stated interoperability path across vendors.
Second-order effects
- Naming two foundries hedges the wafer-supply squeeze Lisa Su described days later, letting AMD shift allocation between TSMC and Samsung as leading-edge capacity tightens.
- Samsung foundry gains a marquee x86-class customer to validate its advanced nodes against TSMC, sharpening the foundries' competition for AMD's future tape-outs.
Third-order effects
- If the chiplet-plus-open-interconnect pattern holds, server silicon consolidates around modular designs where the interconnect standard — not the socket — decides which vendors' dies can combine, rewarding whoever drives CXL adoption.
- The early-node-first posture laid out here matured into AMD claiming first-customer status at TSMC's 2nm node, suggesting a durable structure where AMD trades volume commitments for priority access to each new process generation.
The trend: AMD's recurring CTO roadmap interviews trace its shift from fabless challenger to lead customer of the leading edge, with foundry partnerships and open interconnect standards as the load-bearing choices.