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Chronicles

The story behind the story

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TSMC says its 3nm process will hit volume production in 2022, and 5nm N5 chips, which should ship in products this year, will use 30% less power than the N7

At TSMC's annual Technology Symposium, the Taiwanese semiconductor manufacturer detailed characteristics of its future 3nm process node …

AnandTech Andrei Frumusanu

Context & Ripple Effects

Two months after TSMC began installing 3nm fabrication lines — on track for volume production in H2 2022 per DigiTimes — the company used its annual Technology Symposium to put specifics on both leading-edge nodes: 5nm N5 chips shipping in products this year at a claimed 30% power reduction over N7, and 3nm hitting volume production in 2022.

The symposium framing matters because TSMC was simultaneously committing capital beyond Taiwan, having started construction on a 5nm factory in Arizona while keeping 3nm ramp plans anchored to its home island.

First-order effects

  • Chip designers on TSMC's N7 get an immediate upgrade path: N5 ships in products this year with 30% lower power draw, making the node jump the default choice for new flagship silicon rather than a wait-and-see decision.
  • TSMC's stated 3nm timeline gives customers a planning anchor for 2022 tape-outs, locking the H2 2022 target first flagged when fab-line installation began.

Second-order effects

  • The power-efficiency claims sharpen the node race with Samsung, which TSMC would later trail to 3nm mass production (~35% less power than 5nm) — forcing both foundries to compete on efficiency-per-watt metrics at each node handoff.
  • A two-node transition running concurrently (N5 ramping, N3 tooling up) pressures equipment suppliers and capacity planners, since each new iteration demands fresh cleanroom space like the Arizona 5nm site.

Third-order effects

  • If the cadence holds — and TSMC's own later roadmap extends it, targeting a new client node roughly yearly through 2029 (roadmap through 2029) — foundry leadership consolidates around whoever can fund parallel node development plus geographic expansion, a bar only TSMC and Samsung currently clear.

The trend: Leading-edge chipmaking is settling into a yearly-node treadmill where foundries commit to next-node timelines years out, tying customer roadmaps and multi-billion-dollar fab construction to promised power-efficiency gains.

Discussion

  • @anandtech @anandtech on x
    TSMC's defect rate for its new N5 process is very low - it's currently better than where the N7 process was at this stage of development. The company showcased a few graphs detailing the ramp of N5 and where it's going, including readable numbers! https://www.anandtech.com/... ht…
  • @kaz9837 KaZen on x
    TSMC Details 3nm Process Technology: Full Node Scaling for 2H22 Volume Production https://www.anandtech.com/... Intel fabs will turn into dark cloud
  • @hpc_guru Hpc Guru on x
    TSMC Details #3nm Process - Compared to N5, N3 to improve performance by 10-15% at the same power, or reduce power by 25-30% at the same transistor speeds N3 is planned to enter risk production in 2021 and enter volume production in 2H22 https://www.anandtech.com/... #HPC https:/…
  • @anandtech @anandtech on x
    TSMC Details 3nm Process Technology at its 2020 Technology Symposium: N3 should have a 32% frequency improvement and 51% power reduction over current generation N7 products. Risk production planned in 2021 with mass production in the second half of 2022: https://www.anandtech.com…