Intel details its 3D-stacked Lakefield chips, designed for ultraportable, foldable, and dual-screen devices, in a bid to compete with ARM and Qualcomm
Chaim Gartenberg / The Verge :
Context & Ripple Effects
Lakefield is the productization of a bet Intel has been telegraphing for years: the Foveros 3D-stacking technology it demoed at the end of 2018, which lets logic dies sit atop one another with integrated power delivery. It is also the latest attempt at a problem Intel has circled before — the 2015 SoFIA push tried to get cheap, integrated Atom parts into mobile designs and largely stalled.
First-order effects
- Device makers building foldable, dual-screen, and fanless ultraportables gain an x86 option whose stacked die shrinks the board footprint enough to fit those new form factors.
- ARM licensees and Qualcomm face a direct x86 challenger in the thin-and-light segment they had effectively owned on power efficiency grounds.
Second-order effects
- Qualcomm is pushed to answer on form-factor silicon for PCs and foldables, turning the contest into one of packaging and hybrid core design rather than raw node leadership.
- Advanced packaging shifts from a research showcase to a competitive weapon, forcing rivals to treat stacking and integration as table stakes in client chips.
Third-order effects
- If Lakefield's hybrid, stacked approach holds, it validates the path Intel later took to full disaggregation — the chiplet-based Meteor Lake generation that followed as its answer to Apple silicon — making heterogeneous integration, not monolithic dies, the default architecture for client CPUs.
The trend: Chip competition is migrating from process-node bragging rights to advanced packaging and mixed-core architectures, where whoever integrates best wins the ultraportable market.