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Chronicles

The story behind the story

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New Intel chip flaws disclosed: one can leak secure enclave data and the second allows cross core info leakage; both have patches that partially fix the issues

Intel's speculative execution flaws go deeper and are harder to fix than we thought.  —  For the past two years, modern CPUs …

Ars Technica Dan Goodin

Context & Ripple Effects

This disclosure extends a two-year arc that began when Intel argued the CPU flaws were not limited to its own chips while working with AMD and ARM on fixes ([[a:925432]]). Since then the pattern has repeated: Foreshadow showed speculative execution could breach secure enclaves, and ZombieLoad hit nearly all post-2011 chips, with Apple, Microsoft, and Google shipping performance-costing mitigations.

What makes the new pair notable is that both targets are Intel's most sensitive surfaces — enclave data and cross-core leakage — and that the patches only partially fix them. That follows an earlier finding of an effectively unfixable flaw exposing chipset mask ROM across five years of silicon, deepening the sense that mitigation, not elimination, is the realistic ceiling.

First-order effects

  • Cloud operators and enterprises running enclave-based workloads face immediate exposure to enclave-data leaks and must deploy microcode updates that, as with ZombieLoad's fixes, trade away some performance for partial protection.
  • Intel's patch cadence now covers two more attack classes it cannot fully close, adding to the support burden for customers who have already absorbed multiple rounds of Spectre-class mitigation overhead.

Second-order effects

  • Rivals AMD and ARM, which Intel itself named as co-collaborators on speculative-execution fixes back in 2018, gain a security talking point as buyers re-evaluate which vendor's silicon carries the least side-channel baggage.
  • Software vendors relying on hardware-protected enclaves for secrets management must layer software defenses on top of incomplete microcode, shifting cost onto the application stack rather than the chip.

Third-order effects

  • If each generation of silicon keeps yielding partially fixable speculative-execution flaws, confidential-computing promises built on enclaves weaken structurally, and procurement decisions tilt toward diversifying suppliers — a tailwind for second-source compute strategies beyond any single vendor's roadmap.

The trend: Speculative execution keeps generating partially fixable side-channel disclosures across successive Intel chip generations, steadily eroding confidence in enclave-based confidentiality and pushing security-conscious buyers toward multi-vendor silicon sourcing.

Discussion

  • @lizrice Liz Rice on x
    “the staging buffer contains sensitive data, including the output of the hardware digital random number generator...this vuln can be exploited against victim apps running in Intel SGX secure enclaves...can leak the private key of a secure enclave running on a separate CPU core” h…
  • @nelsonijih Nelson Ijih on x
    .@signalapp and @chainlink among many others promise “confidential computing” because of Intel's SGX's enclaves. Now they're in trouble Perhaps, specially dedicated enclaves in systems(one not integrated into CPU) may be a better alternative for homomorphic encryption https://twi…
  • @aschilling Andreas Schilling on x
    Up to now side channel attacks were limited to one CPU core. With Special Register Buffer Data Sampling aka #CrossTalk some instructions can make access to off-core memory and in combination with RIDL gives access to data across several cores. https://www.vusec.net/... https://tw…
  • @iancoldwater Ian Coldwater on x
    oh my word CrossTalk is sweet af 😍 the first cross-core attack using transient execution! more info here: https://www.vusec.net/... whitepaper here: https://download.vusec.net/...
  • @aschilling Andreas Schilling on x
    There was an embargo for 600+ days on #SRBDS, due to the difficulty of implementing a fix for the cross-core vulnerabilities. Intel deep dive: https://software.intel.com/... Affected CPUs: https://software.intel.com/... https://twitter.com/...
  • @tinkerfairy_net Tinker Fairy on x
    “See https://www.vusec.net/... for complete ready-to-run PoCs” - those 10 words a girl longs to hear. Bravo, @vu5ec https://twitter.com/...