Interview with AMD CTO Mark Papermaster on AMD's release schedule and future products, partnerships with TSMC and Samsung, driving industry standards, and more
Dr. Ian Cutress / AnandTech :
Context & Ripple Effects
This interview sits mid-arc in AnandTech's run of conversations with AMD's technical leadership: it extends the EPYC chiplet strategy Papermaster laid out in late 2018, where 7nm CPU dies were paired with 14nm IO dies, into a broader discussion of roadmap cadence and foundry relationships. A week later, CEO Lisa Su addressed TSMC's tight wafer supply, making clear the capacity behind that roadmap was already constrained.
The TSMC-and-Samsung framing matters because AMD is effectively running a dual-foundry posture while claiming to drive industry standards rather than follow them. Seen against Papermaster's later claim that AMD became the first customer for TSMC's 2nm process (More Than Moore, January 2026), this 2020 conversation reads as an early statement of the foundry-first positioning AMD has since institutionalized.
First-order effects
- AMD's product release schedule is now explicitly coupled to external foundry nodes at TSMC and Samsung, so roadmap credibility rests on foundry execution rather than internal fabs.
- Papermaster positions AMD as a standards driver, which raises the stakes for its chiplet and interconnect choices being adopted by partners rather than treated as proprietary.
Second-order effects
- Tight wafer supply at TSMC, which Lisa Su flagged days after this interview, means AMD's cadence commitments put direct pressure on allocation — every node commitment AMD signs competes with other TSMC customers for the same wafers.
- Samsung's role as a second source gives AMD negotiating leverage on pricing and capacity, while forcing rivals dependent on a single foundry relationship to justify their own supply posture.
Third-order effects
- If the pattern holds, leading-edge silicon consolidates around a small set of fabless designers who commit earliest to new nodes — AMD's claimed first-customer status at 2nm suggests early commitment converts into both supply priority and marketing leadership.
- Standards-setting by a merchant CPU vendor shifts industry structure away from vertically integrated control: interconnects, packaging, and chiplet interfaces become negotiated industry infrastructure rather than one company's design decision.
The trend: Leading-edge chipmaking is consolidating around fabless designers who lock in foundry node commitments earliest, turning foundry relationships — not fab ownership — into the basis of competitive position.