Intel demos Foverus, a new way to build 3D chips by stacking logic chips atop one another, with a new power delivery process, without sacrificing performance
Brian Barrett / Wired :
Context & Ripple Effects
Intel's Foverus demo lands a month after Wired's report that chip makers are turning to chiplets — multiple small pieces of silicon in one package — to keep pace with Moore's Law. Foverus extends that logic vertically: instead of placing dies side by side, it stacks logic chips atop one another and adds a new power delivery process, so the added layers cost no performance.
The demo is the opening move in a line Intel has kept extending: the 3D-stacked Lakefield chips for ultraportable, foldable, and dual-screen devices two years later, then a post-2025 roadmap promising 30%-50% more transistors per area through stacking. Foverus is where that arc starts.
First-order effects
- Intel gains a second performance lever beyond transistor shrinking: stacking logic-on-logic with integrated power delivery lets it add compute density without the usual thermal or speed penalty.
- ARM and Qualcomm face a more credible x86 challenger in ultraportable, foldable, and dual-screen devices, the exact segment Lakefield was built for.
Second-order effects
- Advanced packaging moves from back-end afterthought to front-line differentiator, forcing AMD and other chiplet adopters to compete on stack architecture and power delivery, not just die size.
- Foundry customers get a new reason to pick Intel: a stacking process bundled with leading-edge nodes makes Intel's packaging capability part of the foundry pitch.
Third-order effects
- If the pattern holds, Moore's Law progress decouples from lithography cadence — density gains come from vertical integration of dies, making packaging IP as strategically valuable as process nodes.
- Chip design fragments further into stacked, mixed-technology packages, favoring companies that control both the fab and the interconnect research, as Intel's Foundry Technology Research team signaled in 2024.
The trend: Chip performance scaling is shifting from shrinking transistors on a flat die to stacking them in 3D packages, with power delivery and packaging becoming the new competitive frontier.