A roundup of the 2025 VLSI conference: using digital twins for design exploration, DRAM beyond 1x nm nodes, Intel's 18A process compared to TSMC, and more
Dylan Patel / SemiAnalysis : X: @semianalysis_ X: @semianalysis_ : Intel 18A Details & Cost Future of DRAM 4F2 vs 3D Backside Power Adoption (or Not) China's FlipFET Digital Twins from Atoms to Fabs and More VLSI 2025 Roundup https://semianalysis.com/...
Context & Ripple Effects
VLSI 2025 puts several semiconductor bottlenecks in one frame: logic-process economics, memory-cell scaling, power delivery and the use of digital twins to evaluate choices before committing them to manufacturing. It extends Intel’s earlier research work on interconnect scaling, gate-all-around devices and packaging from lab advances to a broader comparison of production-path trade-offs.
The Intel 18A-versus-TSMC discussion matters because process-node competition is no longer reducible to a nominal node label; cost, manufacturability and power-delivery choices are part of the comparison. The DRAM sessions similarly frame 4F2 layouts and 3D approaches as alternative routes once conventional scaling becomes harder.
First-order effects
- Chip designers and manufacturing teams gain a consolidated set of technical benchmarks for evaluating digital-twin workflows, DRAM architecture paths and advanced logic-process trade-offs.
- Intel’s 18A is subjected to a more explicit cost-and-technology comparison with TSMC, while backside-power delivery is presented as a decision with unresolved adoption conditions rather than an automatic next step.
Second-order effects
- Foundry and memory-roadmap decisions increasingly need to weigh process integration and design enablement alongside density gains; digital twins can shift more iteration into simulation before fab experiments.
- Competing DRAM approaches—continued 4F2 scaling versus 3D DRAM—raise the importance of manufacturing complexity and yield in determining which path is practical, not just the smallest cell geometry.
Third-order effects
- If these discussions translate into deployments, semiconductor progress will become more heterogeneous: logic, memory, interconnect and power delivery may advance on different schedules rather than through a single predictable shrink cadence.
- Digital twins could become a core source of process-development advantage, concentrating value in the data, models and manufacturing feedback loops that connect design choices to fab outcomes.
The trend: The industry is moving from straightforward dimensional scaling toward a portfolio of architecture, integration and simulation-led techniques to keep improving chips under tighter manufacturing constraints.