ASML CFO Roger Dassen says TSMC, Intel, and Samsung will all get its €350M high-NA EUV machines by the end of 2024; the machines can print 8nm lines on chips
- TSMC has previously said ASML's new machine is too expensive — Intel has already received its first high-NA EUV machine
Context & Ripple Effects
ASML had already begun preparing 2024 shipments of its first €350M-class high-NA systems, making the announced deliveries a transition from launch preparation to placement at the three leading logic manufacturers. ASML’s shipment ramp-up put the tool’s availability, rather than its technical debut, at the center of the competitive question.
The early customer list did not settle whether every recipient would deploy the machines immediately in volume production. TSMC had publicly flagged the equipment’s cost as a concern, while Intel had already received its first tool; later coverage underscores that TSMC deferred production use even as Intel moved toward a product deployment.
First-order effects
- TSMC, Intel, and Samsung gain access to ASML’s high-NA EUV platform by the end of 2024, while Intel begins with an early installed-base advantage from its first delivered system.
- ASML converts a small set of leading chipmakers into customers for an exceptionally capital-intensive tool capable of printing 8nm lines, tying its near-term rollout to their installation and qualification plans.
Second-order effects
- The buyers must weigh the potential process benefits against the €350M per-tool outlay; TSMC’s stated reluctance shows that delivery does not automatically translate into production adoption.
- Different deployment speeds can affect foundry positioning: Intel’s later decision to use the tools for Panther Lake illustrates how product-level adoption can turn equipment access into a manufacturing differentiator.
Third-order effects
- High-NA EUV could widen the divide between firms able to fund, integrate, and qualify frontier lithography and those that cannot, but the payoff will depend on production economics rather than purchase announcements alone.
- The pattern points to leading-edge progress becoming more constrained by tool cost and deployment timing: access to scarce equipment matters, while volume use may remain selective and delayed.
The trend: High-NA EUV is becoming a test of whether leading chipmakers can convert expensive, scarce lithography access into economically viable manufacturing advantage.