Intel shows Moore's Law is slowing with plans for a third generation of 14nm chips, delays switch to 10nm process to 2017
Intel confirms tick-tock-shattering Kaby Lake processor as Moore's Law falters — Company will make three generations of 14nm processors, delaying the switch to 10nm.
Context & Ripple Effects
Intel's two-year tick-tock cadence assumed each 'tock' delivered a new process node; this announcement breaks that contract, keeping Kaby Lake on 14nm for a third consecutive generation at the same node while pushing the 10nm switch out to 2017.
What reads here as a one-year slip turned into a pattern the rest of the corpus keeps confirming: the 10nm transition slipped again through repeated Cannon Lake delays, the 8th Generation Core became a fourth 14nm chip, and by 2020 the same slippage had moved upstream to Intel's 7nm rollout running twelve months behind internal targets. This 2015 decision is the first documented data point in that arc.
First-order effects
- PC buyers get another year-plus of 14nm silicon: Kaby Lake ships as an optimization of an existing node rather than a shrink, so gains come from architecture tweaks instead of transistor density.
- Intel's product roadmap loses the tick-tock pacing mechanism that coordinated its CPU launches, forcing planners inside the company and its OEM partners to schedule around process uncertainty rather than a fixed cadence.
Second-order effects
- Rivals still hitting their own node transitions gain a window to close the manufacturing gap Intel's density lead had protected, since Intel's advantage was built on being first to each shrink.
- Foundry customers and OEMs weighing Intel against alternative suppliers now have a concrete data point on execution risk, making multi-sourcing conversations easier to justify.
Third-order effects
- If the pattern holds — and the later 7nm delay suggests it did — the industry's assumption that the leading-edge manufacturer sets the pace gives way to one where process transitions are measured in half-decade slips, reshaping how competitors and regulators evaluate Intel's roadmap claims.
- A decade of node delays culminates in the situation visible in recent coverage: Intel planning 14A and 1nm-class processes for 2026-2027 while raising equity to fund the buildout, meaning the cost of catching up after this 2015 stall is now measured in capital raises, not just calendar quarters.
The trend: Process-node transitions are decoupling from Moore's Law's two-year rhythm at Intel specifically, turning manufacturing execution — not design leadership — into the company's defining competitive constraint across the decade that follows.