TSMC unveils its process technology roadmap through 2029, aiming to launch a new node yearly for client applications and every two years for AI and HPC
Still no High-NA on horizon. … TSMC revealed its general manufacturing technology roadmap through 2029 at its North American Technology Symposium 2026 on Wednesday.
Context & Ripple Effects
TSMC’s earlier roadmaps traced a progression from planned 3nm volume production in 2022 to N2 in 2025, followed by A16 and A14 plans extending into 2028. The 2026 roadmap carries that cadence forward through 2029.
The new distinction is product-specific: annual node introductions for client applications versus a two-year rhythm for AI and HPC, while High-NA EUV remains absent from the disclosed plan.
First-order effects
- TSMC gives client-chip customers a yearly process-node planning cadence through 2029, while AI and HPC customers are positioned around a longer two-year update cycle.
- The roadmap sets expectations that TSMC’s disclosed leading-edge progression will continue without High-NA EUV during this period.
Second-order effects
- Client-device designers can align product refreshes more closely with successive process updates, whereas AI and HPC chip roadmaps may place more weight on architecture, packaging, and system-level gains between node transitions.
- The split cadence makes TSMC’s process roadmap a more explicit constraint on how its customer base segments product planning between high-volume client chips and AI/HPC silicon.
Third-order effects
- If maintained, differentiated node cadences could formalize a bifurcated leading-edge foundry market: faster iteration for client silicon and longer process platforms for AI/HPC systems.
- The lack of High-NA EUV in the published roadmap suggests that progress through 2029 is being framed around the process technologies TSMC has already chosen to disclose, rather than a near-term equipment transition.
The trend: Leading-edge foundry roadmaps are increasingly being tailored to distinct product cycles for client devices and AI/HPC infrastructure rather than presented as one uniform node cadence.