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Chronicles

The story behind the story

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TSMC says its most advanced chip packaging tech, CoWoS, is growing at an 80% CAGR as it ramps up capacity; Nvidia has reserved most of TSMC's CoWoS capacity

An underappreciated step in the chipmaking process is poised to become the next bottleneck for artificial intelligence.

CNBC Katie Tarasov

Context & Ripple Effects

Advanced packaging has been tightening for years: TSMC previously committed to an advanced-packaging facility as AI demand made existing capacity tight, then moved toward panel-level packaging specifications to address rising demand. The latest disclosure makes clear that the constraint has shifted from a supporting production step to a gating resource for AI-system output.

The pressure is also reshaping access to TSMC more broadly. Reports earlier in 2026 said Apple was competing for TSMC capacity amid the AI boom, while later coverage describes advanced packaging as increasingly concentrated in TSMC and its Taiwan partners.

First-order effects

  • Nvidia's reservation of most available CoWoS capacity gives it preferential near-term access to a critical production step, while limiting the immediately allocable supply available to other TSMC customers.
  • TSMC must convert a fast-growing CoWoS order pipeline into installed capacity; packaging throughput, rather than leading-edge wafer fabrication alone, becomes a binding delivery constraint.

Second-order effects

  • AI-chip rivals and large device customers face greater pressure to secure packaging allocations earlier, diversify packaging approaches, or accept slower product-volume ramps when supply is constrained.
  • The bottleneck strengthens the case for alternative high-volume methods such as TSMC's proposed panel-level packaging approach and raises the strategic value of the suppliers and partners needed to expand advanced-packaging output.

Third-order effects

  • If reservations remain concentrated among a few AI-chip buyers, advanced packaging could become a durable source of bargaining power and customer prioritization in the semiconductor supply chain, not merely a temporary manufacturing pinch point.
  • The pattern points to greater systemic exposure to a concentrated packaging base in Taiwan; efforts to add capacity elsewhere may matter, but their ability to relieve the constraint depends on comparable process capability and ecosystem scale.

The trend: AI infrastructure demand is moving the industry’s limiting factor downstream—from chip design and wafer capacity toward advanced packaging and the tightly coupled supply chain around it.

Discussion

  • @katietarasov Katie Tarasov on x
    Advanced packaging - it's a last step in making chips - and the next AI bottleneck. #Nvidia has reserved most of it and 100% of TSMC chips have to be sent to Taiwan for it. Now TSMC is building its first U.S. packaging plants as @elonmusk taps Intel for it https://www.youtube.com…