Q&A with Intel EVP Dr. Ann Kelleher on lessons learned from the company's misadventures with 10nm process nodes, its vision for Foundry Services, and more
It's somewhat of an understatement to say that Intel's future roadmap on its process node development is one of the most aggressive in the history of semiconductor design. Tweets: @iancutress , @keaakre , and @redfire75369 . Thanks: @iancutress Tweets: @iancutress : With this interview, I'm completing my final day here at @AnandTech. It's been a great 10 years working with the team, with @ryansmithAT, @anandshimpi, @bretthowse, @gavbon86 + all. My next venture will be in tech - hope to give more information next week. I'm not going far! 😎🤘 https://twitter.com/... @keaakre : Perfect description of Ann Kelleher: “What I loved about speaking to Ann is the element of quiet but striking determinism in the way she spoke...” Insightful Q&A with Intel's GM of Technology Development. #IAmIntel https://twitter.com/... Redfire / @redfire75369 : Dr. Ann Kelleher on High-NA EUV in I18A (1/4): > We're aiming to introduce it in more in 2025, and we're setting up our processes so that if for some reason High-NA is not ready, then we will be able to continue without it. (...) https://www.anandtech.com/... Thanks: @iancutress
Context & Ripple Effects
This interview is the second of three sit-downs AnandTech-adjacent press ran with Ann Kelleher as Intel's process narrative evolved: she had already walked through the new logic roadmap and lithography plans in August 2021, seven months before this conversation about what went wrong at 10nm. The through-line is that Intel's foundry pitch depends on publicly owning its execution failure — the same 10nm node that finally reached servers in the Ice Lake Xeon generation.
The stakes go beyond retrospection: Kelleher's Foundry Services vision here is the groundwork for the IDM 2.0 foundry push Pat Gelsinger would later defend in his own Q&A on Intel Foundry, Amazon, and 18A, and the roadmap cadence she describes — including High-NA EUV planned for 18A in 2025 with a fallback if it slips — is the credibility test external customers would judge Intel by.
First-order effects
- Kelleher is putting Intel's 10nm failure on the record as a lessons-learned exercise, directly addressing the trust deficit potential foundry customers hold about committing designs to Intel processes.
- The interview positions Foundry Services as a real business line rather than a slogan, giving Intel a public narrative to recruit customers against its aggressive node roadmap.
Second-order effects
- External chip designers weighing Intel as a foundry now have a stated cadence — High-NA EUV at 18A in 2025, with prepared fallbacks — to hold Intel to, making every future node slip a public credibility event for the foundry pitch.
- Intel's own product groups benefit from the same discipline: the 10nm lessons feed the roadmap that its data-center line, rebuilt around 10nm Ice Lake Xeon, depends on staying competitive.
Third-order effects
- If the pattern holds, Intel's identity shifts from integrated device maker to foundry-services competitor, with process-execution credibility — not architecture — as the binding constraint on the whole strategy.
- The arc closes structurally in the 2025 Foundry reorganization that moved Kelleher to strategic adviser ahead of retirement, signaling that the turnaround she describes became an institutional program larger than any one executive.
The trend: Intel is attempting to convert the 10nm execution failure into foundry-market credibility, with node cadence — culminating in 18A — as the proof point for its IDM 2.0 pivot.