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Chronicles

The story behind the story

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Samsung claims it will deliver 3nm chips with gate-all-around transistor tech in 2021, promising they'll be 35% faster and use 50% less power than its 7nm chips

but they'll be more expensive. https://www.cnet.com/... @cnetnews : Shrinking chip circuitry down to 3 nanometers will boost speed 35% while cutting power use 50% in 2021 so your phone battery lasts longer. https://www.cnet.com/... Ben Bajarin / @benbajarin : 3nm! https://twitter.com/...

CNET Stephen Shankland

Context & Ripple Effects

Samsung's 2019 announcement put it on record that gate-all-around transistors would carry it to 3nm a full year before rival TSMC, which had separately told customers its own 3nm process would reach volume production in 2022. The claim was aggressive enough that the follow-on coverage reads as a scorecard: Samsung slipped the timeline to 2022, then delivered anyway.

First-order effects

  • Samsung's foundry customers get a second source for leading-edge 3nm silicon before TSMC's node is ready, though the company itself flagged that these early GAA wafers will cost more.
  • The promised 35% speed gain and 50% power cut versus 7nm set the benchmark every subsequent Samsung node claim gets measured against — including the eventual first mass-production milestone in mid-2022.

Second-order effects

  • TSMC is forced to match the cadence rather than lead it: after Samsung's slip to 2022, both foundries converged on the same year, and TSMC began mass-producing 3nm months later while committing to new 2nm plants in Taiwan.
  • A two-foundry race at each node gives chip buyers leverage on price and allocation that a single-source leading edge never allowed, pressuring both suppliers' margins on next-generation contracts.

Third-order effects

  • Gate-all-around stops being an experiment and becomes the default transistor architecture past finFET limits, anchoring public roadmaps that now stretch to 2nm in 2025 and 1.4nm in 2027 under Samsung's five-year mass-production plan.
  • Power-per-chip displaces raw shrink as the headline metric of node transitions — Samsung touts 45% lower power versus 5nm, TSMC roughly 35% — signaling that battery life and data-center energy budgets, not just density, now drive foundry competition.

The trend: Leading-edge foundry competition is consolidating around gate-all-around transistors, with Samsung and TSMC trading first-mover claims while power efficiency replaces pure scaling as the selling point.