MIT researchers say they've developed a special purpose chip that increases the speed of neural network computations by up to 7x while consuming ~95% less power
New chip reduces neural networks' power consumption by up to 95 percent, making them practical for battery-powered devices.
Context & Ripple Effects
This 2018 result sits at the head of a now decade-long arc in specialized AI silicon. MIT's chip attacked the two costs that dominate neural network inference — compute speed and power draw — and its follow-on work shows the approach wasn't a one-off: two years later the same group built a chip with tens of thousands of artificial synapses (memristor-based design) aimed at image recall on-device.
Since then, the energy-efficiency thesis has moved from academic labs to industrial roadmaps: IBM's brain-inspired NorthPole prototype cut external memory access to slash power, IBM's 2nm process promised 45% more performance at equal power, and startups like Extropic are now claiming order-of-magnitude gains over incumbent AI chips. What was a research demo in 2018 has become the central competitive axis of AI hardware.
First-order effects
- Battery-powered devices gain a credible path to running neural network inference locally, since a ~95% power reduction removes the main obstacle to on-device AI without tethering to cloud datacenters.
Second-order effects
- Cloud AI operators face pressure to adopt similar special-purpose silicon, because workloads that run cheaply at the edge erode demand for centralized inference — a dynamic later reflected in industry efforts like SoftBank and Intel's Saimemory venture targeting stacked DRAM at roughly half the power of current HBM (Saimemory).
Third-order effects
- If the pattern holds, AI compute stratifies into heterogeneous stacks — general-purpose GPUs for training, domain-specific low-power silicon for inference — making energy-per-inference, rather than raw throughput, the metric that determines which architectures win.
The trend: AI hardware is converging on energy efficiency as the defining design constraint, with each successive chip announcement — from MIT's lab demos to IBM's NorthPole and Extropic's probabilistic bits — raising the bar for what counts as efficient inference.