Intel says Facebook is giving technical input for AI chip, called the Nervana Neural Network Processor, expected to ship on a limited basis later this year
Ted Greenwald / Wall Street Journal :
Context & Ripple Effects
This lands a year after Intel laid out an AI roadmap built on Nervana technology that it admitted was incomplete until the Movidius acquisition closed (Intel's 2016 AI chip vision). The limited Nervana Neural Network Processor shipment with Facebook as technical contributor is the first concrete proof point of that roadmap reaching real hyperscale workloads.
The arrangement matters because it cuts both ways: Intel gets a marquee customer shaping its flagship trainer, while Facebook gets a chip tuned to its models — a stepping stone on the path toward the in-house AI chip design team Bloomberg reported it building months later.
First-order effects
- Facebook gains direct influence over a shipping Intel training accelerator, tailoring the NNP to its recommendation and content-serving workloads before committing fleet-wide purchases.
- Intel converts its Nervana bet from paper roadmap to product, using Facebook's involvement as validation against incumbent GPU suppliers for data center training.
Second-order effects
- The co-design template spreads quickly: Baidu signed on as a contributor to the 16nm Nervana for image-recognition training by mid-2019 (Baidu's contribution to the 16nm Nervana), showing Intel recruiting one hyperscaler at a time to anchor each generation.
- Facebook's willingness to shape someone else's silicon sits alongside its parallel effort to design its own ML chips for recommendation and video transcoding (Facebook's internal ML chip development) — meaning Intel's biggest collaborator is simultaneously becoming a potential competitor.
Third-order effects
- If the pattern holds, hyperscalers move from buying merchant AI chips to co-designing them and finally building their own, shifting bargaining power from chip vendors to the handful of companies that operate the largest training fleets.
- Architectural divergence follows: with Nervana dropping a standard cache hierarchy so software manages on-chip memory directly (Nervana's software-managed memory design), co-designed chips optimize for specific customers' frameworks rather than general-purpose compatibility — fragmenting the accelerator market along workload lines.
The trend: Cloud giants are progressing from purchasing AI accelerators to co-designing them with vendors and ultimately building their own silicon, with each Intel Nervana collaboration marking another rung on that ladder.