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Chronicles

The story behind the story

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SoftBank and Intel form Saimemory, a company to develop a prototype within two years of stacked DRAM chips for AI that consume ~50% of the power of current HBM

TOKYO — SoftBank and Intel are developing a type of memory for artificial intelligence expected to consume much less electricity …

Nikkei Asia

Context & Ripple Effects

Saimemory shifts the SoftBank-Intel connection from reported discussions over an AI chip—talks that did not meet SoftBank’s requirements—to a focused memory-development effort. It enters an HBM market already advancing through products such as Samsung’s higher-capacity HBM3E and investments in the packaging needed to stack DRAM dies.

First-order effects

  • SoftBank and Intel now have a dedicated vehicle to pursue a stacked-DRAM prototype with a stated power target relative to current HBM, concentrating their near-term work on memory rather than a complete AI chip.
  • The effort puts power efficiency alongside bandwidth and capacity as a design criterion for AI memory, while leaving commercial viability dependent on achieving the prototype target.

Second-order effects

  • Incumbent HBM suppliers and advanced-packaging players face a clearer incentive to emphasize energy efficiency in addition to stacking density and throughput; SK Hynix’s planned HBM packaging capacity illustrates why packaging is central to that competition.
  • AI-system builders could gain another memory-design path if the prototype succeeds, potentially broadening component choices beyond conventional HBM rather than changing current deployments immediately.

Third-order effects

  • The project supports a longer-term shift in AI infrastructure from optimizing individual accelerators toward co-designing memory, packaging, and compute around power constraints.
  • If lower-power stacked memory proves manufacturable at scale, differentiation in AI hardware may increasingly accrue to integrated memory-and-packaging architectures, not just processor performance.

The trend: AI infrastructure is moving toward memory-centric co-design as power consumption becomes as consequential as raw bandwidth for scaling AI systems.