Imec, one of the top chip R&D companies, reports several breakthroughs for printing logic and memory chips in a joint ASML lab using ASML's new High NA tool
Context & Ripple Effects
The results extend the High-NA test lab ASML and Imec opened in June, which was intended to let customers evaluate the new lithography platform before manufacturing deployments expected in 2025–26.
They also address the longer-running question of how far chip scaling can continue as physical limits on ever-smaller chips become more consequential. Demonstrations spanning both logic and memory make the lab relevant to more than one chip-production path.
First-order effects
- Imec and ASML gain experimental evidence that ASML’s High-NA tool can print relevant logic and memory structures, strengthening the joint lab’s role as a process-development venue.
- Chipmakers evaluating High-NA now have additional published work to assess as they plan process development and eventual production adoption.
Second-order effects
- The results raise the practical pressure on competing fabrication platforms and lithography alternatives to show comparable progress for both logic and memory use cases.
- Early High-NA users, including Intel Foundry after its first commercial High-NA tool assembly, can use Imec’s work as an external signal that process learning is moving from tool installation toward application testing.
Third-order effects
- If these demonstrations translate into repeatable manufacturing processes, leading-edge scaling will depend still more on coordinated toolmaker, research-lab, and fab development rather than on equipment delivery alone.
- That would reinforce ASML’s central position in advanced lithography, while leaving adoption timing contingent on whether customers can justify High-NA’s manufacturing economics.
The trend: High-NA EUV is moving from laboratory access toward cross-category process validation, making collaborative R&D a key gate between new lithography hardware and volume chip production.