Intel unveils its GPU D-series for data centers, featuring up to 480GB of LPDDR5X memory, an unusually large capacity to support demanding inference workloads
Intel GPU D-series uses laptop LPDDR5X with 480GB memory — Intel's GPU D-series sets a new GPU memory record with 480GB of LPDDR5X
Context & Ripple Effects
Intel had already framed its Crescent Island data-center GPU around power- and cost-optimized inference, then detailed an Xe3P design that substituted LPDDR5X for HBM for agentic-AI workloads. The D-series pushes that memory-led positioning much further, making capacity a central product differentiator rather than a secondary specification.
The move also puts Intel’s approach alongside Nvidia’s Vera rack architecture, which uses LPDDR5X on its CPUs. That makes LPDDR5X an increasingly visible part of data-center AI system design, not solely a laptop-memory component.
First-order effects
- Intel gives inference operators a GPU option with up to 480GB of LPDDR5X memory, aimed at workloads whose model and working-memory requirements strain lower-capacity accelerators.
- LPDDR5X becomes a more consequential qualification and sourcing choice for Intel’s data-center GPU customers, because the D-series’ headline capacity depends on it.
Second-order effects
- Nvidia and other data-center accelerator suppliers face a more explicit capacity-versus-memory-technology comparison, as Intel argues that LPDDR5X can support demanding inference workloads without relying on HBM.
- Memory suppliers gain another route into AI infrastructure demand: data-center GPU designs can consume LPDDR5X alongside the server and laptop markets that already use it.
Third-order effects
- If high-capacity LPDDR5X designs prove competitive for inference, AI infrastructure will segment more sharply by workload, with memory capacity, bandwidth, power and cost traded off rather than one memory standard serving every accelerator.
- The shift points toward a more heterogeneous AI hardware stack, where GPUs, CPUs and their attached memory are selected around inference deployment requirements instead of training-led component hierarchies.
The trend: AI inference hardware is broadening beyond HBM-centric accelerator designs as vendors use alternative memory architectures to target capacity, power and cost trade-offs.