Intel will build next-generation chips with 3D structures
Intel said today that it will build its next generation of chips with 3D structures, a move that will allow it to pack much more computing power in a given space and stay on the path of technological advancement for years to come.
Context & Ripple Effects
Intel has spent years framing its roadmap around doing more with less — its 2007 promise that chips would run faster while using less power set the template, and today's move to 3D transistor structures is the engineering answer to how. The company is extending that arc by turning transistors on their side, which lets it keep packing density into each generation even as flat, planar shrinking gets harder.
The scale of the commitment is what separates this from a lab demo: per Engadget's same-day report, Intel plans to mass-produce 3D transistors across all future client CPUs beginning with its 22nm Ivy Bridge line. Coming weeks after confirmed announcements of a shrunken Intel-Micron NAND process, Thunderbolt developer outreach, and USB 3.0 support slated for the 2012 client platform, it signals an Intel pushing hard on every layer of the platform at once.
First-order effects
- Ivy Bridge becomes the first volume CPU built on 3D transistor structures, giving Intel higher transistor density and lower leakage at 22nm — a direct performance-per-watt advantage in the PCs and servers shipping on that silicon.
Second-order effects
- Rivals like AMD and the ARM-based chipmakers chasing Intel's manufacturing lead now have to fund their own transitions away from planar transistors or concede the density race, since Intel has converted a research result into a mass-production commitment first.
- Better performance per watt strengthens Intel's push into battery-constrained devices, where it is still fighting for relevance — including an unconfirmed, reportedly ZTE-built smartphone handset design aimed at getting its chips into phones.
Third-order effects
- If 3D structures prove out in volume, the industry's definition of a process generation shifts from shrinking feature sizes on a flat plane to building upward, making capital-intensive fab leadership an even steeper moat around the few manufacturers who can afford it.
The trend: Transistor scaling is pivoting from planar miniaturization toward three-dimensional structures as the traditional path to Moore's Law gains runs out of room.