Q&A with SiFive co-founder Krste Asanović, who was part of the original team that developed RISC-V, on creating a company that builds IP around RISC-V, and more
Update: SiFive just announced today that it has partnered with NVIDIA for NVLink Fusion on RISC-V. It's a big step, and we'll be covering that separately.
Context & Ripple Effects
SiFive’s business is built around commercial IP based on RISC-V, a path it has pursued since its early chip-design launches and subsequent financing. The interview lands alongside SiFive’s planned NVLink Fusion integration, which would connect its processor-IP platforms to NVIDIA and partner chips.
That development gives the company’s RISC-V strategy a concrete role in heterogeneous systems rather than treating the architecture only as a standalone CPU alternative. It also extends a history of external validation that included Intel licensing SiFive IP for foundry offerings.
First-order effects
- SiFive can position its RISC-V processor IP for designs that need to communicate with NVIDIA and partner silicon through NVLink Fusion, broadening the interoperability proposition for prospective licensees.
- NVIDIA gains a route for RISC-V-based components to participate in NVLink Fusion designs, while customers get an additional IP option for assembling mixed-vendor systems.
Second-order effects
- RISC-V IP rivals and other processor-architecture vendors face pressure to demonstrate comparable interconnect compatibility where customers are building systems around NVIDIA silicon.
- Chip designers evaluating SiFive may weigh interconnect access alongside CPU performance and licensing terms, making ecosystem integration more central to IP-platform selection.
Third-order effects
- If such integrations become common, open instruction-set architectures may compete less as isolated CPU choices and more as components within tightly coupled accelerator-centric platforms.
- The larger question is whether interoperability expands customer design flexibility or concentrates system-level influence around the dominant interconnect and accelerator ecosystem.
The trend: AI hardware is shifting toward heterogeneous compute platforms in which processor IP, accelerators, and high-speed interconnects are selected as an integrated system.