/
Navigation
Chronicles
Browse all articles
Explore
Semantic exploration
Research
Entity momentum
Nexus
Correlations & relationships
Story Arc
Topic evolution
Drift Map
Semantic trajectory animation
Posts
Analysis & commentary
Pulse API
Tech news intelligence API
Browse
Entities
Companies, people, products, technologies
Domains
Browse by publication source
Handles
Browse by social media handle
Detection
Concept Search
Semantic similarity search
High Impact Stories
Top coverage by position
Sentiment Analysis
Positive/negative coverage
Anomaly Detection
Unusual coverage patterns
Analysis
Rivalry Report
Compare two entities head-to-head
Semantic Pivots
Narrative discontinuities
Crisis Response
Event recovery patterns
Connected
Search: /
Command: ⌘K
Embeddings: large
TEXXR

Chronicles

The story behind the story

days · browse · Enter similar · o open

Highlights from IEDM 2025: 3D NAND is suddenly relevant again, interconnect metals beyond copper are emerging, 2D materials that could replace silicon, and more

IEDM 2025 Round-Up  —  It's an odd time in the chipmaking industry.  On one hand, we are ramping into the biggest supercycle ever seen.

SemiAnalysis

Context & Ripple Effects

IEDM’s research agenda now spans memory, wiring and channel materials rather than transistor geometry alone. That extends the prior VLSI discussion of DRAM scaling beyond 1x nodes and Intel’s interconnect-scaling research.

The relevance is heightened by coverage identifying advanced logic wafer availability as an AI bottleneck, making progress across other parts of the semiconductor stack consequential rather than merely academic.

First-order effects

  • 3D NAND, alternative interconnect metals and 2D channel materials receive renewed technical attention from device, process and materials teams; the report signals research momentum, not immediate production substitution.
  • Interconnect scaling becomes a more explicit design constraint alongside transistor scaling, reinforcing the importance of work such as foundry research on new wiring approaches.

Second-order effects

  • Equipment, materials and memory suppliers face pressure to support more heterogeneous process roadmaps if research programs move from demonstrations toward integration.
  • Chip designers may place greater value on memory density and interconnect advances when leading-edge logic capacity remains constrained, as highlighted in coverage of N3 capacity limits.

Third-order effects

  • If these research directions mature, semiconductor scaling will increasingly depend on coordinated advances in materials, memory architecture, interconnects and packaging rather than silicon transistor shrinks alone.
  • The industry’s innovation pipeline may diversify beyond a small set of leading-edge logic nodes, though commercialization timelines and manufacturability remain uncertain.

The trend: This is one data point in the shift from transistor-centric scaling toward whole-stack materials and architecture innovation under AI-driven semiconductor demand.

Discussion

  • @semianalysis_ @semianalysis_ on x
    Interconnects Beyond Copper, 1,000 CFETs, SK Hynix Next-Gen NAND, 2D Materials, and More https://newsletter.semianalysis.com/ ... [image]