AMD says chips with new 3D-stacked L3 cache tech, allowing up to 768MB of total L3 cache per chip, will arrive in Q1 2022 and are in preview now on Azure
AMD CEO Lisa Su unveiled the first details about the company's EPYC Milan-X processors, which come with a 3D-stacked L3 cache called 3D V-Cache … Thanks: @paulyalcorn
Context & Ripple Effects
Lisa Su's Milan-X reveal is the data-center debut of 3D V-Cache: chiplet-stacked L3 that lifts per-chip cache to 768MB, with Microsoft Azure hosting the preview so cloud customers can benchmark latency-bound workloads before the Q1 2022 launch. The related coverage shows this was not a one-off server SKU — within weeks AMD ported the same stacking to desktop in the Ryzen 7 5800X3D, claiming a 15% gaming uplift.
The longer arc holds: by mid-2024 the roadmap had moved to Zen 5-based EPYC Turin on 3nm, and by 2026 AMD was shipping Venice-X with 1,152MB of stacked cache — a 50% jump over Milan-X's ceiling. Cache capacity, once fixed by die size, has become a per-generation scaling axis.
First-order effects
- Azure tenants get immediate preview access to Milan-X instances, letting hyperscale customers validate the 768MB-cache advantage on their own workloads ahead of the Q1 2022 general availability.
Second-order effects
- AMD extends the same single-stack design into the client market with the 5800X3D gaming chip, forcing rivals to answer stacked-cache performance at both the server and desktop price points rather than just one.
Third-order effects
- If the Milan-X-to-Venice-X trajectory holds, package-coupled cache becomes a permanent roadmap tier — each EPYC generation pairing core-count gains with roughly 50% more stacked L3, turning cache capacity into a headline spec alongside cores and clock speed.
The trend: Server silicon is scaling memory-on-package as a first-class lever against the memory wall, with AMD's V-Cache line growing from 768MB to 1,152MB across successive EPYC generations.