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Chronicles

The story behind the story

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Samsung starts mass production of 16GB LPDDR5 DRAM using extreme ultraviolet lithography, says the process clears a “major developmental hurdle” in scaling RAM

Samsung is fond of bragging about its progress on memory chips, but this is one time where it made a particularly notable breakthrough.

Engadget Jon Fingas

Context & Ripple Effects

Samsung announced the LPDDR5 specification back in 2018, targeting 6.4Gbps transfer rates and 30% lower power, and has since shipped successive mobile DRAM generations — including 10nm 12GB LPDDR4X for smartphones in 2019. What changes here is the manufacturing tool, not just the density: extreme ultraviolet lithography entering mass DRAM production, which Samsung frames as clearing a major hurdle in scaling RAM.

The density arc explains why that matters: Samsung's mass production of 8Gb LPDDR4 in 2014 enabled 4GB-RAM phones, and each subsequent node pushed package capacity higher. EUV-based 16GB LPDDR5 is the step that made the later LPDDR5X generation — like the 14nm 16GB LPDDR5X unveiled in 2021 at 8.5Gbps — buildable on top of it.

First-order effects

  • Smartphone makers gain a shipping 16GB LPDDR5 package built on EUL-patterned dies, letting flagship designs double RAM without growing the memory footprint Samsung's later thin-stack work targeted.

Second-order effects

  • With EUV proven in volume DRAM, Samsung's node roadmap accelerates — the LPDDR5X chips it unveiled afterward claim 1.3x the speed and 20% lower power than LPDDR5, raising the bar every rival mobile-DRAM supplier must match.

Third-order effects

  • If EUV keeps migrating from logic into memory lines, DRAM scaling becomes a lithography race rather than purely a cell-design one — favoring manufacturers who can fund the tooling, and pushing mobile devices toward ever-larger RAM as a default spec.

The trend: Mobile DRAM is scaling by importing advanced lithography into memory fabs, with each node migration roughly doubling per-package capacity and setting the baseline for the next LPDDR generation.