JEDEC, which sets mainstream RAM speed standards, releases its final spec for DDR5 SDRAM, with a 6.4 Gbps max data rate, and a 128 GB max UDIMM capacity
Ryan Smith / AnandTech : Tweets: @anandtech Tweets: @anandtech : Today JEDEC is releasing the final DDR5 memory specification to its members. The latest DDR spec will double max memory speeds to DDR5-6400, split DIMMs into two independent 32-bit channels, and allow LRDIMMs as large as 2TB! https://www.anandtech.com/... https://twitter.com/...
Context & Ripple Effects
This closes a three-year loop: back in 2017, JEDEC said DDR5 would land the following year at twice DDR4's speed, and the final specification now fixes exactly what vendors build to — DDR5-6400, two independent 32-bit channels per DIMM, 128 GB UDIMMs and LRDIMMs up to 2 TB.
The spec matters because it converts vendor roadmaps into shippable products: SK Hynix's first DDR5 DRAM chips at 4,800–5,600 Mbps on a lower 1.1V rail and Samsung's 512GB DDR5 modules for advanced workloads are both calibrated against targets this document sets.
First-order effects
- Memory vendors get a frozen interface contract — SK Hynix and Samsung can move from pre-spec silicon to production parts without fearing pinout or timing changes, and platform designers can finally commit motherboards and memory controllers to the dual-channel-per-DIMM layout.
Second-order effects
- The 2 TB LRDIMM ceiling gives server buyers a reason to wait for DDR5 platforms over discounted DDR4 inventory, pressuring module makers to race down the high-capacity path Samsung has already staked out with its record-capacity RDIMM work.
Third-order effects
- Splitting each DIMM into two independent channels shifts system architecture toward finer-grained memory access baked into the standard itself, while mobile's separate LPDDR track — where SK hynix is already pushing far higher transfer rates — confirms client and server memory are evolving into distinct product lines rather than one market.
The trend: Mainstream DRAM standards are advancing on a steady double-the-speed cadence under JEDEC even as mobile LPDDR pulls ahead separately, splitting memory into diverging client and server product lines.