A look at AMD's 25x20 project, which it started in 2014 to improve overall “Performance Efficiency” 25x by 2020, and what its success means in the long run
One of the stories bubbling away in the background of the industry is the AMD self-imposed ‘25x20’ goal. Tweets: @underfox3 and @hpc_guru . Thanks: @iancutress Tweets: Underfox / @underfox3 : In an evident death of Moore's law and all related challenges, it would be foolish to make such a bold proposition for the years to come. But I must agree that the next years will be really fun. 🦊 https://www.anandtech.com/... https://twitter.com/... Hpc Guru / @hpc_guru : .@AMD succeeds in its 25x20 self-imposed goal from 2014 25x20: achieving 25x performance efficiency by the year 2020 By @IanCutress in @anandtech https://www.anandtech.com/... https://twitter.com/... Thanks: @iancutress
Context & Ripple Effects
In 2014, when process-node gains were already flattening, AMD publicly committed to a 25x improvement in overall 'Performance Efficiency' by 2020 — a bet that engineering and architecture could substitute for free transistor scaling. Ian Cutress's retrospective confirms the goal was met, landing right as observers like Underfox note the effective death of Moore's law makes such targets foolishly bold.
That efficiency engine is the throughline for everything AMD did next: it underwrote the Zen-era recovery, the 71% YoY Q1 2022 revenue jump with Enterprise, Embedded and Semi-Custom up 88%, and ultimately the AI-era posture where CEO Lisa Su now forecasts 35%-plus average annual revenue growth and 80% AI data center growth.
First-order effects
- AMD exits 2020 with a quantified, externally verified efficiency claim at precisely the moment node shrinks stop delivering free wins — turning performance-per-watt from an internal metric into a public benchmark its roadmap is judged against.
- The result sharpens AMD's contrast with Nvidia, whose data center position the SemiAnalysis deep dive attributes largely to CUDA software lock-in rather than efficiency credentials.
Second-order effects
- Efficiency credibility compounds commercially: the same execution discipline shows up in accelerating accelerator cadence and open-standards advocacy under Forrest Norrod, plus reported multi-billion-dollar debt raises to fund AI-driven spending.
- Node priority follows efficiency reputation — CTO Mark Papermaster says AMD became the first customer for TSMC's 2nm process, meaning foundry capacity allocation increasingly tracks who can convert transistors into delivered work fastest.
Third-order effects
- If the pattern holds, chip competition reorganizes around published efficiency targets rather than node announcements alone: buyers and investors gain a measurable yardstick, and vendors that can't state one compete on power budgets instead.
- With Moore's-law scaling no longer doing the heavy lifting, sustained per-watt gains depend on architecture-plus-software co-design — which is exactly where AMD's acknowledged ROCm lag versus CUDA becomes its structural vulnerability despite hardware parity ambitions.
The trend: As transistor scaling slows, chipmakers are shifting from competing on process nodes to competing on verifiable performance-per-watt roadmaps, with AMD's 25x20 as the template proof point.