Sources: DeepSeek R2's launch delay is due to training issues on Huawei Ascend chips, prompting a switch to Nvidia chips for training and Huawei's for inference
Difficulties of training the start-up's latest system with Huawei's semiconductors highlight dependence on Nvidia
Context & Ripple Effects
DeepSeek's R2 delay follows earlier reporting that a shortage of Nvidia server chips in China had also constrained the project. The new account adds an execution constraint: Huawei hardware was being tested for training despite prior reports of gaps in its training performance, connectivity and software stack relative to Nvidia.
The reported split between Nvidia for training and Huawei for inference anticipates DeepSeek's later plan to use Ascend for smaller R2 variants while retaining Nvidia for its largest models.
First-order effects
- R2's release is delayed as DeepSeek moves training workloads to Nvidia chips, reinforcing Nvidia as the immediate dependency for its largest-model development.
- Huawei retains an inference role, but the reported training problems limit Ascend's use in the most demanding development workflow.
Second-order effects
- DeepSeek must operate a mixed hardware stack, separating training from inference rather than standardizing on one supplier; this adds integration and deployment complexity.
- The result sharpens pressure on Huawei to improve the training-side software, stability and inter-chip performance identified in earlier reporting on Ascend's training gaps.
Third-order effects
- If this division persists, Chinese AI developers may treat domestic accelerators as a viable inference layer before relying on them for frontier-model training, creating a more durable split between smaller-model and largest-model hardware choices.
- The episode shows that access to chips alone does not remove compute execution risk: software maturity and systems performance can remain the binding constraint even where alternate hardware is available.
The trend: AI developers are increasingly adopting heterogeneous compute strategies, assigning training and inference to different chip platforms as they balance performance, availability and software readiness.