At the 2025 RISC-V Summit in China, Nvidia says CUDA will now be compatible with RISC-V's instruction set architecture, making RISC-V a viable x86 and Arm rival
Yet another alternative. — At the 2025 RISC-V Summit in China, Nvidia announced that its CUDA software platform …
Context & Ripple Effects
Nvidia had already extended CUDA toward Arm CPUs through its earlier CUDA-on-Arm collaboration, making this a further expansion of the software platform beyond the traditional x86 host environment. RISC-V also has meaningful backing in China, where Tencent joined RISC-V International alongside other major local technology companies as a premier member.
The move fits Nvidia's broader effort to make its GPUs easier to deploy beside varied host processors. Its NVLink Fusion interconnect program similarly opened rack-scale configurations to non-Nvidia CPUs and accelerators; CUDA compatibility addresses the software side of that heterogeneity.
First-order effects
- RISC-V CPU developers and system builders gain a clearer path to pair RISC-V hosts with Nvidia GPU computing while retaining CUDA-based workflows.
- Nvidia expands CUDA's addressable host-processor ecosystem, reducing the need for customers to choose x86 or Arm solely for compatibility with its accelerated-computing software.
Second-order effects
- RISC-V vendors can use CUDA readiness as a selling point for AI and high-performance-computing designs, increasing competitive pressure on x86 and Arm in systems where Nvidia GPUs are central.
- Customers evaluating custom or regionally sourced CPUs can separate the host-ISA decision from the GPU software decision more readily, provided implementation support reaches production systems.
Third-order effects
- CUDA is becoming a cross-ISA layer rather than a software advantage tied to one CPU architecture, allowing Nvidia to preserve developer lock-in even as host compute diversifies.
- If other GPU software stacks do not match this portability, the market may consolidate around CUDA at the accelerator layer while competition shifts toward CPUs, interconnects, and integrated system design.
The trend: AI infrastructure is moving toward heterogeneous systems in which accelerator software and interconnects must span multiple CPU architectures rather than enforce a single host platform.