Sources: Huawei is designing its next two Ascend chips around a 7nm architecture, meaning its marquee chips will be stuck with aging tech until at least 2026
Context & Ripple Effects
Huawei’s reported 7nm Ascend roadmap follows its earlier claim that it had developed 14nm chip-design tools, a sign of progress in domestic design capability but also of a wide manufacturing constraint. The company was simultaneously preparing mass production of the Ascend 910C, making the node choice consequential for its AI-compute lineup.
The story puts a concrete horizon on Huawei’s effort to rebuild its chip business after restrictions cut off access to advanced US technology. It also provides the backdrop for later plans to increase Ascend output, where volume growth and leading-edge process progress are separate challenges.
First-order effects
- Huawei’s next two Ascend designs would remain tied to 7nm through at least 2026, limiting its ability to use process-node advances as a near-term route to better AI-chip performance or power efficiency.
- Huawei’s AI-hardware roadmap must place greater weight on architecture, software, and production execution while its marquee chips use an older node.
Second-order effects
- Chinese buyers evaluating Ascend systems must weigh a locally available alternative against the performance-per-watt and supply characteristics of competing AI hardware, rather than assume node parity.
- The constraint increases the strategic importance of manufacturing yield and available capacity: later plans to expand 910C output depend on scaling production as well as designing competitive chips.
Third-order effects
- If the pattern persists, China’s second-source AI-compute push may develop through architectural and system-level workarounds rather than rapid convergence with the leading manufacturing node.
- Export controls can therefore reshape competition from a race for the smallest process toward a race over usable supply, packaging, software compatibility, and workload-specific performance.
The trend: AI-chip self-sufficiency efforts are increasingly being shaped by manufacturing-node constraints, pushing vendors toward heterogeneous system design and supply-scale strategies.