AMD, ARM, Qualcomm, IBM, Huawei, Mellanox, Xilinx agree to develop an interconnect to allow their CPUs, accelerators, and networks to coherently share data
On Monday, seven technology companies announced that they had reached an agreement to develop and implement an interconnect …
Context & Ripple Effects
In early 2016, seven companies that rarely sit on the same side of the table — AMD, ARM, Qualcomm, IBM, Huawei, Mellanox, and Xilinx — agreed to co-develop an interconnect that lets CPUs, accelerators, and network devices share memory coherently. Notably, Intel is absent from the group even though it dominates the server CPUs such an interconnect would serve.
The move reads today as the opening bid in a decade-long standardization race: Intel answered three years later by debuting CXL with Google and Microsoft, the same cast then pushed coherence down to dies with the UCIe chiplet consortium, and in 2024 Intel, Google, Microsoft, and Meta formed the Ultra Accelerator Link group to standardize accelerator-to-accelerator links. Each round has widened the participant list — evidence that the original seven saw the problem before the market did.
First-order effects
- AMD, Xilinx, Mellanox, and Huawei each sell pieces of a server — CPUs, FPGAs, NICs, accelerators — that only work tightly together inside one vendor's design; a shared interconnect makes cross-vendor coherent systems technically possible for the first time.
- IBM and Qualcomm gain a route to keep their server silicon relevant in accelerator-heavy workloads without owning an accelerator franchise of their own.
Second-order effects
- Intel's exclusion sets up the countermove visible in the coverage: launching CXL with Google and Microsoft converts its CPU incumbency into control of the successor standard, forcing the original seven's effort to compete against a spec backed by the largest cloud buyers.
- Cloud operators become the swing constituency — whoever they standardize on determines which interconnect survives, which is why every subsequent consortium (UCIe, Ultra Ethernet, UAL) recruits hyperscalers alongside chipmakers.
Third-order effects
- If the pattern holds, coherent interconnects become defined by rolling open consortia rather than any single vendor's bus — the structural precondition for rack-scale systems assembled from best-of-breed CPUs, accelerators, and networking across vendors.
- Huawei's participation in a 2016 US-centric standards effort also foreshadows the geopolitical fault line that later fragments such consortia, since shared-memory infrastructure standards are exactly where export controls and national compute strategies collide.
The trend: Datacenter interconnects are being rebuilt as open, consortium-defined standards — starting with this seven-company pact and continuing through CXL, UCIe, and Ultra Accelerator Link — shifting coherent computing from a vendor lock-in play to shared infrastructure.