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Chronicles

The story behind the story

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Arm prepares to release its Neoverse V3 and N3 CPU designs to its customers, offering up to 128 cores and more, for server, cloud, and infrastructure

A bit over 5 years ago, Arm announced their Neoverse initiative for server, cloud, and infrastructure CPU cores.

AnandTech Ryan Smith

Context & Ripple Effects

Arm’s server roadmap began with Neoverse N1 and E1 designs for cloud and edge workloads, then expanded through V1/N2 platforms and a V2 design aimed at cloud, hyperscale and HPC workloads.

V3 and N3 move that design cadence into a higher-core-count generation, giving Arm licensees new CPU IP to incorporate into infrastructure chips rather than positioning Arm as the chip vendor.

First-order effects

  • Arm customers can begin building server, cloud and infrastructure processors around Neoverse V3 and N3, with configurations reaching 128 cores or more.
  • Arm broadens the set of licensable CPU designs available to chipmakers targeting performance- and scale-oriented infrastructure deployments.

Second-order effects

  • Cloud and infrastructure chip designers gain another option for differentiating custom silicon, increasing pressure on rival CPU platforms to match performance, efficiency or ecosystem support.
  • System vendors and cloud operators evaluating Arm-based servers will have more potential supplier implementations, though actual availability will depend on licensees’ chip and platform launches.

Third-order effects

  • If licensees translate the designs into volume systems, server CPU competition could shift further from a small set of merchant processors toward differentiated, Arm-based custom silicon.
  • The release reinforces heterogeneous infrastructure as operators pair CPUs with workload-specific accelerators rather than treating the CPU as the sole source of compute differentiation.

The trend: Arm is extending Neoverse into increasingly capable server IP as cloud and infrastructure buyers seek more control over the CPUs underpinning specialized compute fleets.