SK Hynix begins mass producing its 238-layer 3D NAND memory chips with a 2,400 MT/s data transfer rate, up from the prior generation's 176 layers and 1,600 MT/s
The new memory promises speeds of up to 2,400 MT/s. — SK hynix said late on Wednesday that it had begun mass production of its 238-layer …
Context & Ripple Effects
The 238-layer chip closes a gap that has been widening since Micron put 176-layer NAND into mass production back in late 2020 at the same 1,600 MT/s interface speed SK Hynix's prior generation ran. Samsung has since pushed further up the stack with its 286-layer 9th-generation NAND, leaving SK Hynix playing catch-up on density even while it holds 22% of quarterly NAND flash shipments.
The timing matters because SK Hynix is pairing the process node with committed capacity: a roughly $13.3 billion NAND fabrication plant in Cheongju and the $720B Yongin Cluster slated for February 2027 production. The 50% jump in transfer rate also extends the pattern of SK Hynix leading on interface speed rather than layer count alone, as it did with the world's first DDR5 DRAM launch in 2020.
First-order effects
- SSD and controller makers integrating this NAND can now design around a 2,400 MT/s interface, a 50% bandwidth step over the 1,600 MT/s generation without waiting for a new host standard.
- Samsung and Micron face immediate pressure to answer on both axes — Samsung's 286-layer part leads on density while SK Hynix now leads on I/O rate, forcing each to compete on the other's home turf.
Second-order effects
- Higher stacking plus committed new fabs (Cheongju, then Yongin) raise SK Hynix's bit output per wafer just as it plans a roughly $29B buyback, signaling confidence it can absorb the capital cycle rather than cut supply.
- Faster NAND interfaces strengthen the case for flash beyond storage: the later High Bandwidth Flash open specification SK Hynix co-authored with Sandisk builds directly on high-bandwidth NAND, opening an adjacent market against DRAM-adjacent workloads.
Third-order effects
- If the layer-count-and-speed race holds, NAND vendors consolidate around two levers — vertical density for cost-per-bit and interface bandwidth for new markets — and the 22%-share tier of suppliers either matches both or cedes ground on one.
- Flash evolving from bulk storage toward high-bandwidth memory-class roles (as the HBF specification anticipates) would blur the NAND/DRAM boundary and reprice what 'memory' means in system design.
The trend: 3D NAND competition is shifting from pure layer counts toward bandwidth and memory-class applications, with SK Hynix betting new fabs that it can hold both fronts.