Apple's M2 chips appear to have two subtle upgrades, making performance cores more efficient and efficiency cores more performant, helping improve battery life
Many years ago, I used to give a presentation to business school students specifically about the semiconductor industry.
Context & Ripple Effects
Apple launched the M2 in mid-2022 as a headline-spec story — 20B transistors, an 18% faster CPU, 50% more memory bandwidth than M1 — then extended the family with the M2 Pro and M2 Max on a second-gen 5nm process in January 2023. Creative Strategies' read is that beneath those spec-sheet numbers sit two quieter changes: performance cores that sip less power and efficiency cores that do more work.
That framing matters because it reframes the M2 generation as a per-core efficiency play rather than a transistor-count story — a reading that anticipates where Apple took the line next, including the eventual renaming of its CPU core categories alongside the M5 Pro and M5 Max.
First-order effects
- MacBook and Mac buyers of the M2 generation get longer real-world battery life without any change to core counts, clock speeds, or the advertised specs they shop by.
- Apple gains a marketing claim that doesn't depend on a new process node — extracting more from the same 5nm-class silicon while the M2 Pro and Max carry the performance narrative.
Second-order effects
- Rivals shipping x86 laptops are pushed to compete on performance-per-watt rather than peak throughput, since Apple is widening the battery-life gap using the same node generation they share.
- Tuning efficiency cores upward shifts more everyday workloads off the expensive performance cores, letting Apple hold performance-tier pricing while delivering perceived speedups for free.
Third-order effects
- If the pattern holds, chip differentiation migrates from headline specs toward scheduler-level and per-core efficiency engineering — the direction Apple's own later move to relabel its core tiers points toward.
- Heterogeneous core design becomes the durable competitive moat in consumer computing, favoring vertically integrated vendors who control both silicon and OS scheduling over merchant-chip assemblers.
The trend: Consumer silicon competition is shifting from raw transistor counts and clock speeds toward per-core efficiency and heterogeneous workload placement, with Apple's M-series cadence setting the reference point.