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Chronicles

The story behind the story

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China's second-largest chip foundry Hua Hong signs a $6.7B wafer fab deal to produce 65nm, 55nm, 40nm, and other chips, as China pivots away from sub-14nm tech

China's second-largest chip foundry Hua Hong Semiconductor Group, a state-backed semiconductor investment fund and a Wuxi entity signed …

South China Morning Post Che Pan

Context & Ripple Effects

Hua Hong's $6.7B wafer fab deal with a state-backed investment fund and a Wuxi entity is the spending phase of a plan set in motion months earlier, when it won approval for a ~$2.5B Shanghai IPO earmarked for a Wuxi plant. The timing tracks an FT analysis days before the signing arguing Hua Hong is barely affected by US sanctions precisely because it specializes in older nodes — making it Beijing's natural beneficiary.

The pivot away from sub-14nm is a deliberate strategy, not a retreat: mature-node capacity is where Chinese chipmakers can scale without touching restricted tools, and the same playbook later shows up in reports of Hua Hong readying a 7nm process at its Shanghai fab with Huawei's help.

First-order effects

  • Capital from the Shanghai listing and the state-backed fund now flows into a Wuxi fab producing 65nm, 55nm and 40nm wafers — Hua Hong doubles down on the node range where it faces no export-control ceiling.

Second-order effects

  • Rival SMIC, which took $2.25B in state-backed funds for its own factory back in 2020, now competes against a state-favored peer for the same domestic mature-node demand, pushing both toward the reported requirement that new capacity use at least 50% domestically made equipment.

Third-order effects

  • If the pattern holds, China's chip industry bifurcates: sanctioned players like Huawei pull advanced work into retrofitted DUV lines — activity said to expose cracks in US-led export controls — while state money industrializes mature nodes at scale, insulating the sector from further sanctions rounds.

The trend: Chinese state capital is building out mature-node foundry capacity as the sanctions-proof base layer of a self-sufficient chip stack, with advanced-node work pushed into retrofit workarounds.