Apple A6 Die Revealed: 3-core GPU, < 100mm^2
Our good friends at UBM TechInsights sent over the first diffusion images of Apple's new A6 SoC. It's still too early to tell a lot but we have confirmation of a lot of things. The image above shows two 32-bit LPDDR2 memory channels and three GPU cores.
Context & Ripple Effects
The A6 story has been building since TUAW reported in August 2011 that A6 production had begun, but the chip's identity stayed opaque until AnandTech's September 15 teardown concluded it was neither an ARM Cortex-A15 nor an A9 — a custom Apple core instead. Two days later, benchmark results showed the A6 beating Intel's Atom Z2460 in SunSpider, raising the question of what Apple had actually built.
UBM TechInsights' diffusion images now put physical evidence behind those claims: three GPU cores, two 32-bit LPDDR2 memory channels, and a die under 100mm². The pickup across eight outlets — Computerworld, CNET, BGR, MacRumors and others — reflects how much rides on confirming Apple's first fully in-house phone SoC, arriving as the iPhone 5 hits stores with sales reportedly matching a month of iPhone 4S online volume in three days.
First-order effects
- Apple's silicon roadmap is now confirmed as self-directed rather than licensed-core: the die shot validates the custom CPU core claim and shows Apple sizing its own GPU core count, freeing it from ARM Holdings' and Imagination's public roadmaps.
- A sub-100mm² die at iPhone 5 volumes translates directly into per-unit cost and yield headroom — Apple can hold margin while shipping the fastest-performing phone SoC on the market.
Second-order effects
- Rivals still shipping off-the-shelf ARM cores — Qualcomm, Samsung, NVIDIA, TI — now face a competitor whose single-threaded performance leads the segment, pressuring them toward their own custom core programs or aggressive multi-core responses.
- Memory suppliers gain a defined demand signal: two 32-bit LPDDR2 channels is a conservative bandwidth choice, which keeps LPDDR2 pricing stable near-term while signaling Apple will move to wider/faster memory only when its own designs require it.
Third-order effects
- If the pattern holds, mobile SoCs bifurcate into licensed-reference designs for the commodity tier and vendor-custom silicon at the top — with Apple's integration of CPU, GPU, and memory controller setting the template others must match to compete on performance-per-watt.
- Die-size discipline as a stated metric (<100mm²) points toward cost-per-performance becoming the public scoreboard for phone chips, shifting competitive pressure onto process node access and fab allocation rather than core counts alone.
The trend: Smartphone silicon is shifting from licensed reference ARM cores to vendor-designed custom SoCs, with Apple's A6 as the proof that in-house design wins both performance and die economics.