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Chronicles

The story behind the story

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SMIC co-CEO Zhao Haijun says the company raised its prices following negotiations with customers in Q1, and that it will charge more for wafers processed in Q3

China's top foundry, Semiconductor Manufacturing International Corp (0981.HK), said on Friday that AI-related demand would continue …

Reuters

Context & Ripple Effects

SMIC entered the pricing discussions after a Q1 in which revenue grew but higher operating expenses weighed on profit. Its subsequent strong Q2 mature-node orders lifted revenue, net profit and gross margin, giving the foundry a firmer backdrop for charging more in Q3.

Zhao Haijun's warning of memory shortages adds a supply constraint to the demand picture: SMIC is signaling that new memory supply will not quickly relieve pressure on wafer customers.

First-order effects

  • SMIC's customers face higher wafer-processing costs in Q3 after the Q1 negotiations, while SMIC gains a direct route to higher revenue per wafer.
  • SMIC is testing whether its recent order strength can translate into sustained pricing power rather than volume-led growth alone.

Second-order effects

  • Chip customers that cannot absorb SMIC's higher processing charges will have to pass costs through, alter product pricing, or adjust their wafer demand.
  • The price move reinforces the capacity pressure implied by Zhao's memory-supply comments, sharpening the commercial value of available foundry and memory capacity.

Third-order effects

  • If SMIC and other suppliers can hold price increases while new memory supply takes months to arrive, semiconductor procurement becomes increasingly defined by capacity access and contract terms rather than spot pricing.
  • The episode fits a more contracted semiconductor cycle in which AI-linked demand spills into mature-node and memory supply chains, though the durability depends on whether new supply eases the constraint.

The trend: AI-related demand is extending semiconductor pricing power beyond leading-edge chips as constrained capacity raises the cost of securing wafers and memory.