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Chronicles

The story behind the story

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Samsung previews zHBM, which vertically stacks HBM atop AI accelerators, and zNAND-O, built on V-NAND, and unveils the industry's first V10 BV-NAND architecture

Samsung Electronics Co. offered a glimpse of its most advanced memory hardware, touting improved performance and power efficiency …

Bloomberg Yoolim Lee

Context & Ripple Effects

Samsung has been moving through the HBM roadmap from 12-high HBM3E to commercial HBM4 shipments and 12-layer HBM4E samples. Its preliminary HBM4 supply agreement for AMD's MI455X gives that progression a named accelerator customer.

The newly previewed zHBM extends Samsung's pitch beyond supplying memory beside an accelerator to placing it directly atop one, while zNAND-O and V10 BV-NAND broaden the roadmap into NAND architecture. The significance is architectural differentiation, not a disclosed customer deployment.

First-order effects

  • Samsung can position zHBM as a package-level option for AI-accelerator partners, alongside its existing HBM4 and HBM4E supply roadmap.
  • zNAND-O and V10 BV-NAND give Samsung a separate advanced-NAND story rather than tying its AI-memory narrative solely to HBM.

Second-order effects

  • Accelerator buyers assessing conventional HBM4E will have to weigh Samsung's future integrated-memory approach against standalone HBM offerings, shifting comparisons beyond bandwidth and stack height.
  • SK Hynix's stated HBM4E sampling plan is now measured against a Samsung roadmap that emphasizes memory-to-accelerator integration as well as successive HBM generations.

Third-order effects

  • If vertically integrated HBM packages reach production, memory suppliers will compete more directly in accelerator-package design, raising the importance of co-engineering with compute-chip customers.
  • The split between zHBM for accelerator-adjacent memory and zNAND-O on V-NAND points to a memory market segmented by system role rather than a single generic performance race.

The trend: AI memory competition is moving from denser standalone HBM stacks toward memory architectures designed around the accelerator package and distinct workload tiers.