Sources: Google is in talks with Marvell Technology to develop a memory processing unit that works alongside TPUs, and a new TPU for running AI models
Google is in talks with Marvell Technology to develop two new chips aimed at running AI models more efficiently, according to two people with direct knowledge of the discussions.
Context & Ripple Effects
Google’s TPU program began as an in-house machine-learning chip effort and has since advanced through successive generations, including separate training- and inference-oriented eighth-generation products. Related coverage also says Google has been pitching TPUs for use in customers’ own data centers, extending the program beyond internal deployment.
The reported Marvell discussions add a memory-processing component alongside a new inference TPU. Later related reporting points to a disaggregated Icefish design, with Samsung discussed for a memory input-output die and TSMC for the compute engine, making this part of a broader effort to specialize and modularize Google’s AI hardware stack.
First-order effects
- Google would gain a prospective external design partner for an inference-focused TPU and a companion memory-processing unit, while Marvell would move deeper into Google’s custom AI-chip roadmap.
- The proposed architecture targets a current bottleneck directly: moving and handling memory alongside TPU compute rather than treating the accelerator as a standalone chip.
Second-order effects
- A separate memory-processing component would increase the strategic importance of memory-interface and packaging choices in Google’s TPU supply chain, as reflected in the subsequent Samsung and TSMC discussions around Icefish.
- If Google intends to place TPUs in customer data centers, more efficient inference hardware could strengthen its ability to position TPUs against alternative AI infrastructure rather than solely optimize them for Google’s own fleet.
Third-order effects
- The design points toward heterogeneous AI systems in which compute, memory I/O, and other functions are partitioned across specialized silicon and suppliers, instead of concentrated in a single accelerator.
- That modular approach could broaden the set of chipmakers competing for AI infrastructure design wins, though its commercial impact depends on whether the talks become production programs and on customer adoption of TPUs.
The trend: AI-chip programs are shifting from monolithic accelerators toward specialized, multi-supplier systems designed to improve inference efficiency and control memory bottlenecks.