Apple changes its CPU terminology alongside the M5 Pro and M5 Max, renaming “performance cores” to “super cores” and “efficiency cores” to “performance cores”
One of the most surprising parts of Apple's announcement on Tuesday of new M5 Pro …
Context & Ripple Effects
Apple’s M-series messaging has long separated high-throughput and lower-power CPU cores, even as coverage of M2 noted that the two core types were converging in capability. The M5 generation also expanded Apple’s emphasis on on-chip acceleration through Neural Accelerators in each GPU core.
The M5 Pro and M5 Max launch pairs the vocabulary change with Apple’s new Fusion Architecture and GPU Neural Accelerators. That makes the naming shift relevant as a signal of how Apple wants buyers to interpret mixed-core compute, rather than as evidence by itself of a new CPU capability.
First-order effects
- Apple’s product pages, launch materials, and future chip comparisons will describe the former efficiency-core tier as “performance cores,” while reserving “super cores” for the former performance tier.
- Customers and reviewers comparing M5 Pro/Max with earlier M-series chips must translate the labels before treating core-category names as like-for-like performance claims.
Second-order effects
- Software and benchmarking coverage will need to distinguish Apple’s renamed categories from any underlying architectural changes, reducing the usefulness of shorthand core-count comparisons across generations.
- The M5 Pro/Max positioning can put more attention on the combined CPU, GPU, and accelerator system rather than a simple performance-versus-efficiency CPU split.
Third-order effects
- If Apple sustains this terminology, heterogeneous mobile processors may increasingly be marketed as tiers of performance rather than as a trade-off between speed and efficiency.
- That framing could make architectural disclosures and real-world measurements more important for buyers evaluating mixed-core chips, since marketing labels alone will convey less about power behavior.
The trend: This is one data point in the broader shift toward presenting heterogeneous, AI-oriented silicon as an integrated performance stack rather than as discrete low-power and high-performance components.